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Thread: Fast implementation of gzip in FPGA

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    Member SolidComp's Avatar
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    Fast implementation of gzip in FPGA

    I thought this paper was interesting – alternative methods of implementing gzip in an FPGA. It took the author only one month using MaxJ. The abstract makes it sound like gzip is implemented in hardware all the time, particularly in FPGAs. I've only heard of a couple of companies that offered gzip accelerator chips (I don't know if they're ASIC or FPGA), and I've never actually seen one in a datacenter. In general, my impression has been that hardware-accelerated or hardware-based solutions are woefully underutilized in the software industry, IT, data centers, etc. Am I wrong? Are there a bunch of people using accelerator chips?

    I've never heard of MaxJ. See the intro below (in-line links aren't working for this for some reason). It's horrifying that it's based on Java, but I guess it could be a lot better than Verilog or whatever.

    http://www.st.ewi.tudelft.nl/~varban...3_Session2.pdf

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    Administrator Shelwien's Avatar
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