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Skylake-X has less L3 cache than predecessor due to cache "rebalancing":
It has larger L2s, and data in L2s are excluded from L3, so L3 can be smaller.
Updated Intel Optimization Manual with Skylake Server info and new chapter on AVX512 optimization:
More info about Skylake-SP and EPYC:
The Following 2 Users Say Thank You to Bulat Ziganshin For This Useful Post:
encode (14th August 2017),Shelwien (14th July 2017)